In recent years, attention has been paid to an MOSFET and an IGBT as a switching element or an inverter controlling element. FIG. 25 is a plan view showing a conventional typical semiconductor device constituted as the MOSFET. In a semiconductor device 151, an insulating layer is formed on an upper main surface of a semiconductor substrate 71 and a gate pad 86 and a source pad 99 for an electrical connection to an outside are formed thereon. FIG. 26 is a partial enlarged plan view showing the enlarged vicinity of a gate pad 82 in FIG. 25. A source electrode 81 connected to a source pad 99 is provided around the gate pad 82. The source electrode 81 is connected to the semiconductor substrate 71 through a plug 92 penetrating the insulating layer.
FIG. 27 is a sectional view showing the semiconductor device 151 taken along a cutting line C-C in FIG. 26. As shown in FIG. 27, the semiconductor device 151 comprises the semiconductor substrate 71, an insulating layer 77, a gate electrode 79, a conductive layer 80, the source electrode 81, the gate pad 82 and a drain electrode 84. The semiconductor substrate 71 includes an N+ type high concentration drain layer 72, an N− type drain layer 73, a P type main base region 74, a P type underpad base region 75 and an N+ type source region 76. The semiconductor substrate 71 is a silicon substrate having an upper main surface and a lower main surface.
The drain layer 73 is formed in the upper main surface of the semiconductor substrate 71. The main base region 74 is selectively formed in the drain layer 73 to be shallower than the drain layer 73 and is exposed to the upper main surface. The underpad base region 75 is selectively formed in the drain layer 73 to be shallower than the drain layer 73 and is exposed to the upper surface. The underpad base region 75 is not coupled to the main base region 74 but is isolated from the main base region 74.
The source region 76 is selectively formed in the main base region 74 to be shallower than the main base region 74 and is exposed to the upper main surface. The main base region 74 is divided into a plurality of regions, and similarly, the source region 76 is arranged by a division into a plurality of regions corresponding to the regions of the main base region 74. The source region 76 is not formed in the underpad base region 75. Accordingly, a channel region is not present in the underpad base region 75. The high concentration drain layer 72 is coupled to the lower main surface side of the drain layer 73 and is exposed to the lower main surface of the semiconductor substrate 71.
The source electrode 81 is formed of metal and is connected to the main base region 74 and the source region 76, and furthermore, is connected to the underpad base region 75 through the plug 92 penetrating the insulating layer 77. The gate electrode 79 is formed of polysilicon and is buried in the insulating layer 77 to be opposed to a channel region in the main base region 74 which is interposed between the drain layer 73 and the source region 76 with a gate insulating film 78 to be a part of the insulating layer 77 provided therebetween.
The gate pad 82 is formed of metal and is provided on the insulating layer 77 to be opposed to an exposed surface of the underpad base region 75 in the upper main surface of the semiconductor substrate 71 with the insulating layer 77 provided therebetween. The gate pad 82 is connected to the conductive layer 80 through a plug 83 buried in the insulating layer 77. The conductive layer 80 is connected to the gate electrode 79 through a path which is not shown. The conductive layer 80 is formed of polysilicon and is buried in the insulating layer 77 to be opposed to the upper main surface in a position closer to the upper main surface of the semiconductor substrate 71 than the gate pad 82. The drain electrode 84 is formed of metal and is connected to the lower main surface of the semiconductor substrate 71.
FIG. 28 is a profile of a resistivity in the drain layer 73 and the high concentration drain layer 72 in the semiconductor substrate 71. As shown in FIG. 28, the resistivity is changed like a step in a coupling portion of the drain layer 73 and the high concentration drain layer 72, and is almost uniform in an inner part of each of the drain layer 73 and the high concentration drain layer 72. The profile results from the formation of the semiconductor substrate 71 in accordance with the steps shown in FIGS. 29 and 30. More specifically, in a process for forming the semiconductor substrate 71, a substrate corresponding to the high concentration drain layer 72 is first prepared and the drain layer 73 is then formed by an epitaxial growth method.
Since the semiconductor device 151 is constituted as described above, an operation is carried out in the following manner. When a grounding potential is applied to the source electrode 81, a positive potential is applied to the drain electrode 84 and a gate voltage which is equal to or higher than a threshold voltage is applied to the gate electrode 79 in this state, an inversion layer is formed in the channel region of the main base region 74. As a result, a current flows through the channel region so that the semiconductor device 151 to be an MOSFET is turned ON. If the gate voltage is caused to have a value which is equal to or smaller than the threshold voltage, the inversion layer disappears. Therefore, the semiconductor device 151 is brought into an OFF state.
In the semiconductor device 151, the main base region 74 and the underpad base region 75 are electrically connected to each other through the source electrode 81. Accordingly, a diode to be provided in the MOSFET is formed by a PN junction between the main base region 74 and the drain layer 73 and a PN junction between the underpad base region 75 and the drain layer 73. When the semiconductor device 151 is set in the OFF state, a backward bias is applied to the built-in diode. A voltage to be applied between the source electrode 81 and the drain electrode 84, that is, a drain voltage is held by a depletion layer expanded from the PN junction of the built-in diode toward an inner part of the drain layer 73 when the semiconductor device 151 is set in the OFF state.
When a positive voltage is applied to the source electrode 81 based on an electric potential of the drain electrode 84 in such a state that the source electrode 81 and the gate electrode 79 are short-circuited, a hole is injected from the main base region 74 and the underpad base region 75 which are connected to the source electrode 81 into the drain layer 73. At the same time, an electron is injected from the high concentration drain layer 72 connected to the drain electrode 84 into the drain layer 73. As a result, a current flows from the source electrode 81 to the drain electrode 84. In other words, the built-in diode is brought into the ON state.
Next, when a negative voltage is applied to the source electrode 81 based on the electric potential of the drain electrode 84, the hole remaining in the drain layer 72 is moved to the source electrode 81 and the remaining electron is moved to the drain electrode 84. As a result, a transient current flows from the drain electrode 84 to the source electrode 81. A mobility of the hole is approximately half of that of the electron. Therefore, a time at which a transient current value becomes zero is equal to a time taken until the hole remaining in the drain layer 73 is annihilated. An operation for damping the current flowing transiently in the semiconductor device 151 down to zero is equivalent to a reverse recovery operation of the built-in diode (that is, a recovery operation).
A hole generated in the conduction of the built-in diode depends on areas of the main base region 74 and the underpad base region 75 and their impurity concentrations. It is a matter of course that the area of the underpad base region 75 provided under the gate pad 82 disposed in order to implement an electrical connection to an outside is larger than that of each of the regions obtained by dividing the main base region 74. Accordingly, the remaining hole is generated in a larger amount in the vicinity of the underpad base region 75 than the vicinity of the main base region 74. Therefore, when the built-in diode is caused to carry out the reverse recovery operation with high di/dt, the hole remaining in the vicinity of the underpad base region 75 convergently flows into a specific portion in the main base region 74 which is close to the underpad base region 75 and flows out toward the source electrode 81 through the specific portion. At this time, a parasitic bipolar transistor formed by the source region 76, the main base region 74 and the drain layer 73 is conducted in some cases. More specifically, in the conventional semiconductor device 151, there is a problem in that a tolerance to a change rate di/dt of the current in a process for the reverse recovery operation, that is, a di/dt tolerance is small.
In the semiconductor device 151, furthermore, in the case in which high dV/dt (a change rate of a voltage with the passage of time) is applied to the PN junction between the base regions 74 and 75 constituting the built-in diode and the drain layer 73, for example, in the case in which high dV/dt of approximately 1 kV/μs or more is applied between the drain electrode 84 and the source electrode 81 with the source electrode 81 and the gate electrode 79 short-circuited, a depletion layer is instantaneously expanded in the PN junction between the base regions 74 and 75 and the drain layer 73. At this time, since a hole is generated depending on an area of the PN junction and a speed at which the depletion layer is expanded, a large number of holes are generated around the underpad base region 75 occupying a large area. A current obtained by the generated hole convergently flows into a specific portion in the main base region 74 which is close to the underpad base region 75. As a result, the parasitic bipolar is conducted in some cases. More specifically, the conventional semiconductor device 151 also has a problem in that the di/dt tolerance is small, and furthermore, a tolerance to a change rate dV/dt of the voltage, that is, a dV/dt tolerance is small.
In the semiconductor device 151 shown in FIG. 27, it is also possible to assume a technique for suppressing the conduction of a parasitic bipolar transistor by forming a third base region including no source region 76 between the main base region 74 and the underpad base region 75. However, when di/dt is increased, the hole remaining in the vicinity of the underpad base region 75 flows into the third base region, and furthermore, convergently flows into a specific portion in the main base region 74 which is close to the third base region and flows out toward the source electrode 81 through the specific portion. Consequently, there can be generated such a phenomenon that the parasitic bipolar transistor is conducted. Similarly, there can be generated such a phenomenon that the parasitic bipolar transistor is conducted when dV/dt is increased.
In order to obtain a great di/dt tolerance or a great dV/dt tolerance, moreover, the area of the main base region 74 in which a current flows with the semiconductor device 151 set in the ON state is decreased if a large number of third base regions are formed. More specifically, a channel width over the whole semiconductor device 151 is reduced. As a result, there is another problem in that an ON resistance is increased.